1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, more particularly, to a semiconductor device including a gate structure for threshold voltage modulation in transistors, and a method for fabricating the same.
2. Description of the Related Art
If a transistor is scaled down to improve the performance thereof, gate leakage increases as the thickness of a gate dielectric layer becomes thin. In order to cope with this concern, the material of a gate dielectric layer is replaced with a high-k material that has a dielectric constant larger than the dielectric constant of SiO2. The high-k material may include a metal oxide containing hafnium, a metal oxide containing zirconium or the like. However, the introduction of the high-k material may have resulted in a Fermi level pinning effect. This effect is caused due to contact between the gate dielectric layer of the high-k material and a polysilicon gate electrode. Fermi level pinning is a basic characteristic of an interface between a polysilicon gate electrode and a metal oxide layer, and tends to increase the threshold voltage of a transistor.
Recently, in order to overcome the Fermi level pinning, a gate stack including a high-k material layer and a metal gate electrode has been suggested. However, it may be difficult to form metal gate electrodes with an N type work function and a P type work function, which require threshold voltages (Vt) appropriate for respective transistors, in a fabrication process of a CMOS device. Also, even when metal gate electrodes with work functions appropriate for respective transistors are formed, the effective work functions of gate stacks may be changed due to various factors that are raised in terms of the material of a gate dielectric layer a gate stack forming process (for example, an etching process and a thermal process at a high temperature) and so forth.